1. Field of the Invention
The present invention relates to a multilayer wiring substrate in which via holes are formed in interlayer insulation layers each isolating a lower conductor layer from an upper conductor layer, and via conductors are formed in the respective via holes for connecting the lower conductor layer and the upper conductor layer, as well as to a method of manufacturing the multilayer wiring substrate.
2. Description of Related Art
In recent years, in association with a size reduction in electrical equipment, electronic equipment, etc., a reduction in size, and densification are required of multilayer wiring substrates to be mounted on such equipment. Practicalized multilayer wiring substrates are manufactured by a so-called build-up process in which resin interlayer insulation layers and conductor layers are alternatingly laminated together (refer to Patent Documents 1 to 3). In the multilayer wiring substrates, a lower conductor layer formed on the lower surface of a resin interlayer insulation layer and an upper conductor layer formed on the upper surface of the resin interlayer insulation layer are connected through via conductors formed in the resin interlayer insulation layer.
In manufacture of the above-mentioned multilayer wiring substrates, via holes are formed in each resin interlayer insulation layer by means of laser machining; the upper surface of the resin interlayer insulation layer is subjected to electroless copper plating, copper electroplating, etc.; and unnecessary portions of the plating are etched away. As a result, an upper conductor layer is formed in a desired pattern on the upper surface of the resin interlayer insulation layer, and via conductors for connecting the upper conductor layer and a lower conductor layer are formed in the respective via holes. The surface of the resin interlayer insulation layer is roughened to become a rough surface, thereby ensuring adhesion between the surface and a conductor layer.
Other than the above-mentioned laser machining method, a practicalized method of forming via holes uses a publicly known technique of lithography and is composed of an exposure step, a development step, etc., (refer to, for example, Patent Documents 2 and 3).
Lands greater in diameter than the via holes are formed on respective upper ends of the via conductors which partially constitute the upper surface of the resin interlayer insulation layer. The via conductors are connected to respective patterned wiring lines of the conductor layer through the lands.
Meanwhile, when the surface roughness of a resin interlayer insulation layer 101 (see FIG. 17) increases, in a copper plating process for forming patterned wiring lines 102 (a conductor layer), copper which is plated for forming the patterned wiring lines 102 is deposited in pits 103 on the surface of the resin interlayer insulation layer 101, and copper 102a deposited in the pits 103 is in such a condition as to project outward from a specified range of a wiring line width W1 (see FIG. 17). In this case, such a condition is an obstacle to high-density disposition of the patterned wiring lines 102. Thus, in recent multilayer wiring substrates, the surface roughness of the resin interlayer insulation layer 101 is decreased from conventional degrees of roughness, thereby implementing high-density disposition of the patterned wiring lines 102.